SPI Flash Memory IC SPI Nor Flash Memory Chip

Pin Configuration

Features

Family of SpiFlash Memories

– 8M-bit / 1M-byte, 16M-bit / 2M-byte, 32M-bit / 4M-byte, 64M-bit / 8M-byte, 128M-bit / 16M-byte 

– 256-byte per programmable page

– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold

– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold

– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3

Highest Performance Serial Flash 

– 50MHz Dual SPI / Quad SPI clocks

– 100/200MHz equivalent Dual/Quad SPI

– 25MB/S continuous data transfer rate

– Up to 4X that of ordinary Serial Flash

 – More than 100,000 erase/program cycles

– More than 20-year data retention

Efficient “Continuous Read Mode”

– Low Instruction overhead

– Continuous Read with 8/16/32/64-Byte Wrap

– As few as 8 clocks to address memory

– Allows true XIP (execute in place) operation

– Outperforms X16 Parallel Flash

– Low Power, Wide Temperature Range

– Single 2.3 to 3.6V supply

– 4mA active current, <1µA Power-down (typ.)

– -40°C to +85°C operating range

Flexible Architecture with 4KB sectors

– Uniform Sector Erase (4K-bytes)

– Uniform Block Erase (32K and 64K-bytes)

– Program one to 256 bytes

– Erase/Program Suspend & Resume

Advanced Security & Identification Features

– Software and Hardware Write-Protect

– Top/Bottom, 4KB complement array protection

– Power Supply Lock-Down and OTP protection

– 64-Bit Unique ID for each device

– Discoverable Parameters (SFDP) Register

– 3X256-Byte Security Registers with OTP locks

– Volatile & Non-volatile Status Register Bits

Space Efficient Packaging

– 8-pin SOIC 150/208-mil